UNIVERSITY OF IDAHO

DEPARTMENT OF MATHEMATICS

COLLOQUIUM

SPRING 2017

Thursday, March 2, 3:30-4:20 pm, room TLC 249

Refreshments in Brink 305 at 3:00 pm

Analog Spiking Neuromorphic Circuits and Systems for Cognitive Computing using Emerging Devices

Vishal Saxena

Department of Electrical and Computer Engineering

University of Idaho


Recently, U. S. Office of Science and Technology announced a grand challenge that called to "Create a new type of computer that can proactively interpret and learn from data, solve unfamiliar problems using what it has learned, and operate with the energy efficiency of the human brain." The current explosion in deep-learning applications is expected to hit a dual wall-(1) plateauing in CMOS scaling, and (2) limits set for energy consumption in a data center. This calls for setting aside the digital von Neumann paradigms for computing and look at analog alternatives by deriving inspiration from the human brain. Spiking neural networks have made steady progress to provide alternative low-power approaches to deep-learning; however, the gains derived from deploying them on digital platforms are not substantial. Large-scale integration of nanoscale emerging devices, such as the resistive RAM (or RRAM) devices in large crosspoint array format, with CMOS, can enable a new generation of Neuromorphic Computers that can solve a wide range of machine learning problems. Such mixed-signal Neuromorphic architectures will result in several orders of magnitude reduction in energy consumption. Several studies, including by the presenter, have been performed using RRAMs as non-volatile "analog" synapses in spiking neural network implementations. However, the progress in this area has been impeded from the realization that the actual RRAM devices fall well short of the expected behavior from the idealized behavior. Based upon the recent results, the presenter will discuss the challenges associated with these devices, their emulation using compact CMOS circuits; architectures that bridge hybrid CMOS-RRAM circuits with spiking neural network algorithms, and their use in neuromorphic system-on-a-chip that can implement large scale deep-learning. Further the presenter will introduce proposed pathways to overcome these challenges to realize Neuromorphic System-on-a-chip (NeuSoC) and extend them to large networks using CMOS photonic interconnects.

Recently, U. S. Office of Science and Technology announced a grand challenge that called to "Create a new type of computer that can proactively interpret and learn from data, solve unfamiliar problems using what it has learned, and operate with the energy efficiency of the human brain." The current explosion in deep-learning applications is expected to hit a dual wall-(1) plateauing in CMOS scaling, and (2) limits set for energy consumption in a data center. This calls for setting aside the digital von Neumann paradigms for computing and look at analog alternatives by deriving inspiration from the human brain. Spiking neural networks have made steady progress to provide alternative low-power approaches to deep-learning; however, the gains derived from deploying them on digital platforms are not substantial.

Large-scale integration of nanoscale emerging devices, such as the resistive RAM (or RRAM) devices in large crosspoint array format, with CMOS, can enable a new generation of Neuromorphic Computers that can solve a wide range of machine learning problems. Such mixed-signal Neuromorphic architectures will result in several orders of magnitude reduction in energy consumption. Several studies, including by the presenter, have been performed using RRAMs as non-volatile "analog" synapses in spiking neural network implementations. However, the progress in this area has been impeded from the realization that the actual RRAM devices fall well short of the expected behavior from the idealized behavior. Based upon the recent results, the presenter will discuss the challenges associated with these devices, their emulation using compact CMOS circuits; architectures that bridge hybrid CMOS-RRAM circuits with spiking neural network algorithms, and their use in neuromorphic system-on-a-chip that can implement large scale deep-learning. Further the presenter will introduce proposed pathways to overcome these challenges to realize Neuromorphic System-on-a-chip (NeuSoC) and extend them to large networks using CMOS photonic interconnects.