Please bring your own paper, pencils, and erasers to each exam. No electronic devices permitted.

120 minutes, closed book, closed notes.

Primary Topics (Chapters 1-3, 5)

Chapter 1

• Digital design representations (e.g., truth table, schematic, equation, etc.)
• Computers and information representation
• Number representation in different bases and base conversion
• Unsigned and signed integers (2's complement)
• Unsigned and signed arithmetic (addition and subtraction)
• Overflow rules for signed and unsigned arithmetic
• Different codes and their properties (e.g., Gray, 1-hot, etc.)
• Primitive gates: (NOT, AND, OR, NAND, NOR, XOR, XNOR, tri-state)
  1. Symbol
  2. Truth table
  3. Boolean expression

Chapter 2

• Switching algebra (axioms, single-variable, two-variable theorems)
• Minterms and maxterms
• Cannonical SOP and POS expressions
• Sigma and Pi notation
• Minimum SOP and POS expressions
• Analyzing a circuit to determine function
• Minimization using switching algebra, Karnaugh maps, don't cares
• Circuit manipulations (bubble cancellation, AND/OR vs. NAND/NAND)
• Timing analysis and static hazards
• Timing diagrams
• Decoders, Encoders, Tri-states, Multiplexers, comparators, and adders
  1. symbols
  2. function
  3. gate-level schematic
  4. application

Chapter 3

• Bistable elements and metastability
• Latches, flip-flops, and registers
• Enables, synchronous sets/resets
• Sequential Circuit to state table/graph
• Circuit/table/graph to timing waveforms
• Problem description to state table/graph
• State table/graph to sequential circuit
• Transition table and equations
• State assignment (binary, Gray, (almost) 1-Hot)
• Synchronous design methodology
• Circuit timing, clock skew, synchronizers
• Parallelism: Spatial and temporal
  

Chapter 5

• Sequential building blocks (counters, etc.)
  1. function and implementation
  2. timing
  3. function table
• Combinational building blocks (adders, comparators, shifters, etc.)
• Memory arrays: SRAM, DRAM, ROM
• Logic arrays: PLAs, FPGAs
  
• Algorithms to Systems using HW Threads (datapath + FSM)
  

 

Not on exam: CMOS transistors (1.7), Transistor-level Latch/FF Design (3.2.7), Derivation of resolution time (3.5.6), VHDL (Ch. 4), Prefix adders (5.2.1), multiplication/division (5.2.6-7), Fixed/Floating Point Number Systems (5.3)