Homework 1

1. Exercises 1.1 and 1.3 (SV) (but not constrained to structural!)
2. How does the Zynq architecture differ from "traditional" FPGAs? (e.g. Spartan 3E)
3. What resources are provided in the PL of the Zynq?
4. What type of interface is available between the PS and the PL in the Zynq?