Homework 2

1. Provide a state diagram (or graph) of a Mealy FSM for controling the original GCD datapath (DPI). Your design must match the cycle timing for loading the initial values of X and Y presented in class, i.e., X loads on the clock cycle after Load is asserted and Y on the next clock cycle.
2. Now construct a cycle timing diagram (i.e., waveforms), that shows the following when computing the GCD of 6 and 4: clock, all inputs, the FSM state, all internal control and status signals, and the values of X and Y.
3. Exercise 2.1 (SV)
4. Exercise 2.3 (SV)