Homework 3

1. Describe in your own words what is meant by a "user defined type" and how we might use it in writing synthesizable code.
   
2. Discuss the difference between these two statements and the synthesis implications.
1. enum {WAITE, LOAD, READY} state;
2. enum logic [1:0] {WAITE, LOAD, READY} state;
3. Would you consider SystemVerilog to be a "strongly typed" language? Explain.
4. What two major toolsets are used in the design flow for a Zynq and how are they used?
5. What is the difference between a BIT file and an ELF file and how are they used?