ECE 440 - GCD Core with a Mealy Controller
Objective
Develop
a synthesizable SystemVerilog model of the GCD design presented in
class, but using a Mealy finite state machine (FSM) as a controller for
the datapath with two
subtractors (DPII). The Mealy FSM should have the same
load timing as the class design and Homework 2. However, modify your
controller to leave the DONE signal asserted once a calculation has
completed until either the RST signal or the LOAD signal is asserted.
(The design can commence with a new calculation without requiring
a"hard" reset.) Assume an 8-bit
datapath.
Specifics
- Verify your model using behavioral simulation (pre-synthesis), displaying the state variables in "symbolic" form
- Synthesize your model and perform post-synthesis functional simulation
Deliverables (upload to Canvas a single PDF file as an attachment, ordered as shown)
- A brief, professional report outlining your approach and identifying any
problems you encountered (first)
- Screen
captures of your behavioral and post-synthesis simulations (bonus
points if someone figures out an alternative to screen captures!)
- Synthesis report
- All source code, including your testbench(es) (last)