Midterm Topics (Readings, Lectures, HW, and Projects)

50 minutes, 100 points. Closed book, open handwritten notes.

Please bring your own paper, a ruler, pencils, and erasers.  No electronic devices permitted.

Primary Topics

Design

• Word problem to block diagram - The Design Process
• Using FPGAs, HDLs, and simulation
• EDA Tools and the Design Flow

Digital logic review

• Info representation
• Combinational logic design
• Combinational building blocks (mux, decoders, etc.)
• FSM design
• Other sequential circuits (e.g., counters, shift registers)
• Timing analysis (setup, hold, Xilinx timing analysis)
• Datapath and control: Design and Analysis
  

Digital Design

• Problem description --> Block diagram (with FSM graph) <---> SystemVerilog
• Digital design using building blocks (i.e., datapath block diagram)
• Datapath vs. Control
• Finite state machine design and analysis
• Mealy vs. Moore, registered outputs
• Sequential circuit and system timing (no pipelining)
• Synchronization and crossing clock domains
• Handshaking (implementation and efficiency)
  

Memories

• Basics of synchronous and asynchronous memory accesses (Xilinx Distributed and Block Memory)
• Synchronous and asynchronous FIFOs
  

SystemVerilog Basics

• operators
• continuous assignments
• use of the always statement
• blocking versus non-blocking signal asisgnments
• structural modeling
• simple testbenches