Week	|	Topic	|
------	|	---------------------------------	|
1	|	Design Choices & Methods	|
2	|	Verilog Intro & Logic Review	|
3	|	Continuous vs. Procedural	|
4	|	Comb vs. Seq Logic Modeling	|
5	|	Finite State Machines	|
6	|	Datapath vs. Control	|
7	|	Testing & Verification	|
8	|	Memory Interfacing	|
9	|	Hierarchy	|
XXXXX	|	Spring Break!!!	|
10	|	Pipelining & Multicycling	|
11	|	Crossing Clock Domains	|
12	|	Reset Strategies	|
13	|	On-Chip Buses and Networks	|
14	|	Beyond RTL	|
15	|	I/O, Trans. Lines, & PCB	|
16	|	No Exam Week	|
17	|	Finals Week	|