AXI Traffic Generator to Stream FIFO to Factorial!

Use the AXI Traffic Generator to write five values of n into an AXI Stream FIFO. (This is instead of writing a C program via the SDK.) An interface module (that I sometimes refer to as "XFACE") will recognize when the FIFO contains data, read that data, and pass it to the factorial module to compute n!. The value of n! will be captured in a separate output register and presented to GPIO. (The output register should be cleared when a computation is initiated, and loaded upon completion.) Perform post-synthesis timing simulation with the following values for n: 4, 6, 8, 10, and 12. Computations must be performed successively, with no resets between calculations.

The traffic generator is synthesizable, in which case you can generate a synthesizable model of the block diagram and perform a post-synth simulation. We won't actually do the Implementation portion of the Xilinx flow, so you can leave your Factorial module as 32-bits.

The "nice" (?) thing about this project is that you can simulate in pieces, working your way up, starting with your factorial module. (Which hopefully will be working from the previous project!). Then, after studying the FIFO interface, design the XFACE module that will "present" the value of n to the factorial and then wait for completion before submitting another, assuming the FIFO isn't empty. Simulate that, connected to the factorial. Next, it may be feasible to simulate a FIFO attached to the XFACE by instantiating it in an SV "top" module (as opposed to the block diagram). Once all that is working, then develop a block diagram that includes the traffic generator. Alternatively, you can just plop the traffic generator and FIFO down on a block diagram, along with a custom IP containing XFACE, etc. as shown here.

Your XFACE and factorial should be clocked by the AXI bus clock, so no need for synchronizers!

Some info on AXI Stream and the AXI FIFO are located under the class handouts for your convenience. (AMBA Protocols/AXI-Stream and AMBA Protocols/Xilinx Docs)

Deliverables

Share your entire project tree, including the IP repo via a folder on your UI OneDrive account by the due date. Upload the assessment and  post-synthesis timing simulations in PDF format to Canvas by Apr 26. (No report!)