Using the IP packaging tools, create
a factorial
co-processor using only addition (no multipliers!) and connect it to
an AXI-Lite interface in a Zynq SoC design. The co-processor is clocked
by the PL clock (125 MHz), not the AXI bus clock. Develop a C
program
using the SDK to demonstrate the functionality of the co-processor
system. A sample C program showing how to include "print" statements is
provided here. (but using a different functional spec)
You will utilize two, 32-bit memory-mapped
registers, Reg0 and Reg1, to pass data between the two domains.
Writing to Reg0 will load n into the register, clear Reg1, and initiate
a handshake with the factorial module. When the computation is
complete, the factorial module will load the result into Reg1 where it
can be read by the CPU. At that point, the co-processor is ready for another operation.