Generate, Store, Sort, and Output

Objective

Generate pseudorandom numbers using an external clock, store them in a block memory for sorting using the Zynq PL clock, and then output the sorted numbers using SPI.

Specifics

Use a 4-bit, maximal cycle LFSR to generate values between 0 and 14, inclusive. Your LFSR should be clocked (carefully!) from the Analog Discovery module using one of the standard PMOD connections, JE1 (V12). (Referred to as je[0] in the master XDC file.) Make sure your waveform is properly configured before connecting to the Zybo! (Alternating between 3.3 and 0 V.) The LFSR continues to run, with FF mapped to the LEDs. Use BTN0 as your reset signal.

Once Switch 0 is asserted, LFSR values are written sequentially into a block memory using the Zynq PL clock, and the LEDs continue to reflect the LFSR values. Only the eight most recent LFSR values are retained in the block memory.

When Switch 0 is deasserted, the system stops storing values and proceeds to sort the eight most recent values in the block memory. During sorting, only LED3 is lit.

Once sorting is completed, the system proceeds to outupt the sorted values, largest first, via SPI. While the SPI transfer is active, only LED0 is lit.

Once transfer is completed, the system returns to the reset state, with the LFSR generating numbers but not writing to the BMEM.

Deliverables

Part A - Implement the LFSR and the writing to block memory. To avoid optimizing away your block memory, route the BMEM output to JE7-10. Upload a single PDF to Canvas showing two behavioral sims capturing the BMEM contents: (a) one the BMEM is full and (b) after the three oldest samples were replaced. Include in the PDF a copy of your code and synthesis report.

Part B - Combine Part A with implementation of sorting the BMEM data. Upload a single PDF to Canvas showing two behavioral sims capturing the BMEM contents: (a) one the BMEM is done capturing, but unsorted, and (b) after the captured values have been sorted. Include in the PDF a copy of your code and synthesis report.

Part C - Add the SPI output functionality to your system to complete the desired functionality. Share your entire project via OneDrive and upload a single PDF file to Canvas showing the SPI output (4-bit hexadecimal data) using both the "Logic" tool and the "Protocol" tool, and a discussion of the state of your project, e.g., works perfectly, appears to be dead, sort of works. (The latter requires elaboration.)

Operate the SPI bus in Mode 1 at ~200 kHz and transmit the most significant bit first for each byte
Chip Select (CS)/Slave Select (SS) is active low and should be asserted at least half of a symbol period before the first bit and remain asserted for at least the same interval after the last bit is transmitted. It should remain asserted throughout the transmission the complete set of sorted numbers.
Use the following signal assignment for JE: (CS-JE2); (SCLK-JE3); (MOSI-JE4). Refer to the Zybo reference manual/schematic. NOTE: the Zybo XDC file starts numbering at 0!!!. Instead, assign CS to pin W16 on the Zynq package.
See this page for SPI decoding using Waveforms, albeit for 8-bit data.