Micron Technologies,
Boise Idaho
Micron Professorship Grant
(2005-2009)
This project, funded as
Micron Professorship Grant, has the goals to study the electrochemical
deposition of copper in vias and trenches coated with tantalum as copper
diffusion barrier. With the development of ultralarge-scale integration (ULSI)
circuits, low resistivity and good elctromigration resistance have become
critical requirements for interconnect materials. Chip level metallization
and particularly the extensive interconnect network that carries signals
between the individual transistors have been fabricated exclusively of
aluminum and aluminum copper alloys by vapor phase techniques. However this
situation has undergone dramatic change after striking IBM’s announcement in
1998/99 by which the company will replace the conventional vapor deposited
aluminum by electroplated copper. Despite initial skepticism, the industry
has adopted the copper plating process into chip fabrication. Never ending
need for chip miniaturization requires thinner lines and smaller nodes, thus
the conductivity is of essential importance. Copper is the second best
known conductor, but its problem is diffusion into silicon matrix destroying
a device (transistor, for example). For that reason, prior to copper
electroplating, the silicon/silicon oxide substrates have to be precoated
with very thin films acting as copper diffusion barriers. The industry is
using/studying various copper diffusion barriers, TaN and TiN being the most
popular.
There are many research challenges on this project,
such as: copper electroplating in deep vias and trenches, copper
electroplating on diffusion barriers (with and without prior copper
seeding), adhesion of diffusion barriers, adhesion of copper lines onto the
diffusion barriers, morphology of copper deposits, conductivity/resistance
of copper lines, integrity (deposits without voids) of copper lines and vias,
copper grains structural distribution, chemistry of the plating bath and
electrodeposition, and so on.
