ECE 440 – Digital Systems Engineering (Spring 2024)

• Course Description
• Course Syllabus  and Schedule (approximate)
• Academic Support Services

Policies

All assignments are due by the start of class on the specified due date, unless otherwise noted. Written assignments will be submitted by uploading a single PDF file to Canvas. Zybo projects will be submitted as a shared folder from the students UI OneDrive account. Attendance is mandatory. Students who miss five or more class periods will automatically receive a final grade of F.

Text

Logic Design and Verification Using SystemVerilog (reviesed), Donald Thomas., ISBN-13: 978-1523364022. March 2016

Supplemental Text

The Zynq Book and the Tutorials (free PDF download available)

Reading

• Jan 10 - chapters 1  and 2 of the SystemVerilog text (SV) and chapters 1 and 2 of the Zynq Book (ZB)
• Jan 17 - chapters 3 and 4 (SV)
• Jan 24 - chapter 3 (ZB)
• Jan 26 - chapter 5 (SV) and Xilinx application note on LFSR
• Jan 28- Xilinx Distributed Memory slides and Xilinx Distributed Memory Generator
• Jan 29 - Xilinx Block Memory slides and Generator
• Feb 2 - Watch this video on inserting Vivado Debug cores and chapter 6 (SV)
• Feb 5 - Read this paper on synchronization errors
• Feb 15 - Synchronous FIFO intro   nd asynchronous FIFO
• Feb 21 - Cliff Cummings' paper on  asynchronous FIFO design
• Mar 22 - Download the tutorials book and source from the Zynq Book site. Read through Section 1, "First Designs on Zynq", and watch this video.
• Mar 29 - Review Section 3.2  and read Chapter 19 of the Zynq Book
• Apr 3 - Designing a Custom AXI-lite Slave Peripheral
• Apr 6 - Read chapter 7 (SV)
• Apr 13 - Read chapter 9.1-2 (SV)
• Apr 22 - Read chapter 10 (SV)
  

Homework and Quizzes (10%)

Homework should be uploaded to Canvas as a single PDF file before class on the date specified below unless stated otherwise There may also be unannounced quizzes periodically, perhaps even daily! It is your responsibility to make sure you are prepared for every class.

1. Due Jan 12. HW1
2. Due Jan 19. HW2
3. Due Jan 26. HW3
4. Due Feb 2. Upload a PDF of a neatly drawn block diagram for the "wrapper" portion of Project 3. You may find some of the OneDrive handouts on the Design Process useful at some point.
5. Due Feb 7. Analyze this amusing little circuit and explain how the memory contents are modified as the circuit goes through four complete cycles of the the four-bit counter. Upload your explaination to Canvas as a single PDF e-mail attachment that includes timing waveforms to illustrate your explaination.
6. Due Feb 9. Attend Career Fair on Feb 7 and bring some sort of company literature/business card to class.
7. Due Mar 20. Upload to a PDF of a neatly drawn block diagram of your approach for Genomatic, along with a written summary of your approach. Be sure to identify any necessary state machines and completely label all status and control signals with recognizable names. (See project 9)
   

Projects (65%)

There will be projects throughout the semester, selected to complement the lectures. Projects must be submitted using the same software version as used in the lab, BEL 215. Students must work independently and contact the instructor if they have questions. No collaboration is permitted. See Sample reports under OneDrive.

1. Due Jan 22. Complete lab1 of the Vivado Design flow on the Zybo board and upload the following deliverables to Canvas as a single PDF file: The Vivado Messages window with all but "status" selected, and the Vivado Synthesis Report. You can download the necessary source files here.
2. Due Jan 29. Project 2
3. Due Feb 5 (by 2:30 pm PT). Project 3
4. Due Feb 12 (by 2:30 pm PT). Create a synthesizable model of the amusing little circuit using distributed memory and perform a behavioral simulation, monitoring primary I/O and internal signals, then repeat with post-implementation simulation observing PIO only. (be sure to simulate through four full counter cycles.) Verify that the memory accesses are the same between the two simulations. Please upload to Canvas a single PDF of your SystemVerilog code, the simulations, and a brief commentary on your experience and observations.
5. Due Feb 17 (10 pm).  Add a debug core to your Project 3 and capture the values of the X and Y registers in decimal when computing the GCD of 0x5F and 0xA1. Upload a single PDF with the captured screenshot(s) to Canvas. No explanation or report required unless your design isn't working. Note: Dr. J encourgages the use of the following debounce module and the "bypass" method (lines 12-18).
6. Due Feb 25 (10 pm). Part A
7. Due Mar 2 (10 pm). (Part B)
   
8. Due Mar 9 (10 pm). (Part C)
9. Due Mar 24 (10 pm).  Genomatic. Share project archive through OneDrive by the due date and upload a brief report (PDF) within 24 hours.
10. Due Apr 1. Carefully follow the steps in Exercise 1A-C from the The Zynq Book and verify on a ZYBO. (Download both the PDF of the tutorials and the Source ZIP file.) See Dr. J's Lessons Learned for "gotchas!" Submit the following screenshots as deliverables: the block diagram of your Processing System from Vivado; top portion of the hdf and mss file/tabs; and the SDK log window (after you have launched the debugger). Paste them all into a single PDF file like this. Upload the file to Canvas. (Mine was for the Zedboard.)
11. Apr 8. Complete Exercise 4A out of the Zynq Tutorial Book (2ed) on the Zybo, but using Verilog. Zip your entire folder and share via OneDrive. Upload to Canvas a PDF of the completed Block Diagram and the terminal window (Figure 4.21). More Gotchas!
12. Apr 17 (10 pm). Factorial Co-processor.
13. Apr 24 (10 pm). AXI Traffic Generator-Stream FIFO-Factorial
14. May 3 (10 pm) - Factorial Verification. Perform a post-synthesis timing simulation of your factorial module using the Vivado simulator with randomization, assertions, and functional coverage! Upload a PDF of the simulation output by 10 pm PT.

Exams (25%)

There will be two exams: a midterm and a comprehensive final, weighted equally. Handwritten material permitted, but no printed material unless otherwise specified, i.e., open notes/closed "book".  Please bring your own paper, pencils, and an eraser to each exam. No electronic devices permitted.

1. Mar 8. Topics
   
2. May 7, Tues, 3-5 pm
   

Class Handouts

On OneDrive.

Reference Material